Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

RingBuffer (FIFO) for C (e.g. for STM32)

Implementation of a circular queue in hardware using verilog.

A ring buffer (FIFO) library for C and C++

In this project, I investigate and design a NoC system consisting of the router/switch, IPs (CPU or other hardware module), and interconnection structure (topology) such as Mesh.

FSM based SPI/SSP Master and Slave Verilog Module

Simple and lightweight FIFO\LIFO buffer library for the Arduino.

Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL

FIFO Buffer Implemented in VHDL

advanced UART IP core on Spartan-3E FPGA using Verilog, featuring FSM-based TX/RX logic, FIFO buffering, and configurable baud rate generation, built and tested on Ubuntu Linux using Xilinx ISE.

Designed an Asynchronous FIFO based on Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons

Designed a synchronous FIFO inspired by the paper Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons