Move QEMU executables to a non-default member `test-qemu`, and add multi-hart tests by KushalMeghani1644 · Pull Request #382 · rust-embedded/riscv

KushalMeghani1644 · 2025-12-22T11:34:12Z

This PR tends to resolve #311.

As requested this PR moves the QEMU executables to a test-qemu non-default member, with a smarter set of tests features that would allow us to execute tests in supervisor mode, machine mode, single hart, multi hart.

…ti-hart tests

romancardenas

Thanks for your PR! I'm currently on holidays, so I cannot do a proper review. You can address this first batch of comments in the meantime

romancardenas · 2025-12-26T18:42:09Z

riscv-rt/examples/qemu_uart.rs

-//! UART example for QEMU virt machine
-//!
-//! This example demonstrates direct UART output on QEMU's virt machine.
-//! It writes to the NS16550-compatible UART at 0x1000_0000.
-


Please, put back the docs, I think they are valuable

romancardenas · 2025-12-26T18:42:16Z

tests-qemu/examples/qemu_semihosting.rs

@@ -1,8 +1,3 @@
-//! Semihosting example for QEMU


Please, put back the docs, I think they are valuable

tests-qemu/examples/multi_hart.rs

romancardenas · 2025-12-26T18:50:45Z

tests-qemu/examples/multi_hart.rs

+        while !HART0_READY.load(Ordering::Acquire) {
+            core::hint::spin_loop();
+        }


I think this handshake is not necessary: HART 1 will not reach main until it receives an interrupt provoked by HART 0 at line 127.

romancardenas · 2025-12-26T18:51:37Z

tests-qemu/examples/multi_hart.rs

+        HART0_READY.store(true, Ordering::Release);
+
+        // Small delay to allow Hart 1 to reach wfi() in _mp_hook
+        // This is needed because we can't use atomics in assembly _mp_hook
+        for _ in 0..100000 {
+            core::hint::spin_loop();
+        }


I think this is not necessary. Just initializing the UART and triggering an interrupt should be enough

romancardenas · 2025-12-26T18:53:08Z

tests-qemu/examples/multi_hart.rs

+    // Enable machine software interrupts
+    li t0, 8            // MIE.MSIE bit
+    csrs mie, t0
+
+1:  wfi                 // Wait for interrupt
+    // Check if software interrupt pending
+    csrr t0, mip
+    andi t0, t0, 8      // Check MSIP bit
+    beqz t0, 1b         // If not set, keep waiting


Maybe, at this point, it is better to use polling with interrupts disabled, so interrupts are not triggered?

romancardenas · 2025-12-26T18:54:23Z

tests-qemu/build.rs

+    let memory_x = match (s_mode, multi_hart) {
+        (true, _) => include_bytes!("memory-s-mode.x").as_slice(),
+        (false, true) => include_bytes!("memory-m-mode-multihart.x").as_slice(),
+        (false, false) => include_bytes!("memory-m-mode.x").as_slice(),
+    };


Does S mode affect the linker file? I think only multi-hart is relevant. We only need two linker files: one for single hart and one for multi hart

Also, as it is now, multi hart is only compatible with M mode right? we could add here a check

Well @romancardenas the S mode linker file is indeed needed, I can't remove it otherwise the S-mode tests fail :(

At-least from what's visible in my local tests, therefore I have kept it.

Yes, I know you need a linker file, but this linker file can be the exact same as in M mode. We only need two linker files: memory.x and memory-multihart.x

romancardenas · 2025-12-26T18:56:15Z

tests-qemu/Cargo.toml

+[features]
+default = ["m-mode", "single-hart"]
+s-mode = ["riscv-rt/s-mode", "single-hart"]
+m-mode = []


We can remove this feature

KushalMeghani1644 · 2025-12-27T11:59:49Z

DONE! @romancardenas I have tried to address all of your comments here... I apologize if I missed something.
Anyways Happy Holidays :)

romancardenas

Thanks!

romancardenas · 2026-01-06T11:27:00Z

tests-qemu/build.rs

+    let memory_x = match (s_mode, multi_hart) {
+        (true, _) => include_bytes!("memory-s-mode.x").as_slice(),
+        (false, true) => include_bytes!("memory-m-mode-multihart.x").as_slice(),
+        (false, false) => include_bytes!("memory-m-mode.x").as_slice(),
+    };


Yes, I know you need a linker file, but this linker file can be the exact same as in M mode. We only need two linker files: memory.x and memory-multihart.x

romancardenas · 2026-01-06T11:37:26Z

tests-qemu/memory-s-mode.x

+MEMORY
+{
+    RAM : ORIGIN = 0x80200000, LENGTH = 16M
+}
+REGION_ALIAS("REGION_TEXT", RAM);
+REGION_ALIAS("REGION_RODATA", RAM);
+REGION_ALIAS("REGION_DATA", RAM);
+REGION_ALIAS("REGION_BSS", RAM);
+REGION_ALIAS("REGION_HEAP", RAM);
+REGION_ALIAS("REGION_STACK", RAM);
+INCLUDE link.x


this file is not required, use memory.x instead

The memory-s-mode.x linker file cannot be replaced with memory.x because OpenSBI loads the payload at 0x80200000, not 0x80000000. I did initially delete it but I had to restore it since the tests just fail.

romancardenas · 2026-01-06T12:02:23Z

.github/workflows/qemu.yaml

+          - example-features:
+              features: "s-mode"
+            target-qemu:
+              target: riscv32i-unknown-none-elf
+          - example-features:
+              features: "s-mode"
+            target-qemu:
+              target: riscv32im-unknown-none-elf
+          - example-features:
+              features: "s-mode"
+            target-qemu:
+              target: riscv32imc-unknown-none-elf
+          - example-features:
+              features: "s-mode"
+            target-qemu:
+              target: riscv32imac-unknown-none-elf
+          - example-features:
+              features: "s-mode"
+            target-qemu:
+              target: riscv32imafc-unknown-none-elf


Can you try this instead?

Suggested change

- example-features:

features: "s-mode"

target-qemu:

target: riscv32i-unknown-none-elf

- example-features:

features: "s-mode"

target-qemu:

target: riscv32im-unknown-none-elf

- example-features:

features: "s-mode"

target-qemu:

target: riscv32imc-unknown-none-elf

- example-features:

features: "s-mode"

target-qemu:

target: riscv32imac-unknown-none-elf

- example-features:

features: "s-mode"

target-qemu:

target: riscv32imafc-unknown-none-elf

- example-features:

features: "s-mode"

target-qemu:

qemu: riscv32

romancardenas · 2026-01-06T12:11:50Z

xtask/src/main.rs

+    let smp_arg;
+    if multi_hart {
+        smp_arg = "2".to_string();
+        qemu_args.push("-smp");
+        qemu_args.push(&smp_arg);
+    }


Suggested change

let smp_arg;

if multi_hart {

smp_arg = "2".to_string();

qemu_args.push("-smp");

qemu_args.push(&smp_arg);

}

if multi_hart {

qemu_args.push("-smp");

qemu_args.push("2");

}

KushalMeghani1644 · 2026-01-08T10:02:19Z

Thanks!

Move QEMU executables to a non-default member, test-qemu, and add mul…

1b6b400

…ti-hart tests

KushalMeghani1644 requested a review from a team as a code owner December 22, 2025 11:34

KushalMeghani1644 marked this pull request as draft December 22, 2025 11:37

Fix CI failing

9d45dbd

KushalMeghani1644 marked this pull request as ready for review December 22, 2025 11:54

KushalMeghani1644 changed the title ~~Move QEMU executables to a non-default member, test-qemu, and add multi-hart tests~~ Move QEMU executables to a non-default member test-qemu, and add multi-hart tests Dec 24, 2025

romancardenas reviewed Dec 26, 2025

View reviewed changes

KushalMeghani1644 added 2 commits December 27, 2025 15:07

Address review

209053f

Fix CI failing

b8aee79

KushalMeghani1644 requested a review from romancardenas December 27, 2025 11:58

KushalMeghani1644 added 2 commits December 29, 2025 21:52

Address review

cc5a1a4

revert

149c39c

romancardenas requested changes Jan 6, 2026

View reviewed changes

address review

73f1a1c

KushalMeghani1644 requested a review from romancardenas January 7, 2026 01:50

romancardenas approved these changes Jan 8, 2026

View reviewed changes

romancardenas added this pull request to the merge queue Jan 8, 2026

Merged via the queue into rust-embedded:master with commit d0893ea Jan 8, 2026
165 checks passed

KushalMeghani1644 deleted the update_qemu_ci branch January 8, 2026 10:02

Comments

Conversation

KushalMeghani1644 commented Dec 22, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

romancardenas left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

KushalMeghani1644 Dec 27, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

KushalMeghani1644 commented Dec 27, 2025

Uh oh!

romancardenas left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

KushalMeghani1644 commented Jan 8, 2026

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

KushalMeghani1644 commented Dec 22, 2025 •

edited

Loading

KushalMeghani1644 Dec 27, 2025 •

edited

Loading