Fix DRC problems. #153
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Fix DRC problems. #153
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* New: In ProtectRoutindPads/checkForLoopHV(), was only checking to
align one non-pref with one reduced. Now also manage two non-pref
to realign them (when both are going the same direction).
* In Anabatic::Configuration::selectRpComponent(), now perform two full
consecutives tries with the VIA12 bottom extensions rotated 90 degrees.
Instead of making one try with a firstly guessed value.
The previous approach was making on-grid terminal considered as
off-grid, leading to too much initial wiring (one uneeded dogleg).
* In pyproject.toml, the lock was now quite old and was still using the
cross_platform strategy which starts to be removed on some newer
systems.
Also remove reference to Rob Taylor homebrew patches that seems
to also have been removed.
* New: In Anabatic: move _postProcessRoutingPads() from Katana to Anabatic
so it could be executed at the right stage. That is, after
chain reducing (cascaded reduction of null-length segment).
* New: In Anabatic, now split the StageDriving stage in two:
- StageChainReduce which compact the null-segments.
- StagePostProcessRoutingpads to handle VIAs too close on
a same RoutingPad. The difference is that, in that stage,
no mimimal length/area should be performed.
Used in AutoSegment::revalidate().
* New: In Anabatic::checkForLoopHV(), now manage two more cases:
- Two non-prefs too close on the RoutingPad.
- Two prefs too close on the RoutingPad.
* Fix: In SegmentFsm CTOR, ignore terminal weight when sorting track cossts
in pack stage. This was in rare case desaligning segments leading to
the creation of loops.
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A preview of 5f6c2c6 is uploaded and can be seen here: ✨ https://lip6.github.io/coriolis/pull/153/ ✨ Changes may take a few minutes to propagate. Since this is a preview of production, content with |
* Fix: In AutoSegment::_makeDogleg() and AutoVertical, ensure that the
initial position of the dogleg axis is on-grid. In some rare case
with IHP SG13G2, it was not. This was then bleeding into extension
cap computation for minimum area/length, finally generating offgrid
shapes.
* Change: In designflow.tasyagle, change the OSDIdll parameter that was
managing one OSDI compiled library into a list of libraries named
TasYagle.OSDIdlls.
Update the calcCPath.tcl script so it takes that changed
parameter into account.
* Change: In designflow.klayout.ShowDRC, this rule no longer depends
of the ".lyrdb". A dependency on ".lyrdb" was implying that the
"drc" rule was successful to be run. But IHP has changed the
behavior of run_drc.py which now return an error code if the
DRC contains errors, effectively preventing "showdrc" to be reached.
* Change: In designflow.task & designflow.clean, manage deletion by
glob for ordinary targets (not "extras"). To allow a more thorough
directory scrubbing at clean stage.
* New: Anabatic::ReduceCluster, find all the reduced perpandiculars to
an aligned set of segments, and detect if they are too close, that
is, less than one perpandicular pitch, if so, align them on the
left most which as a same layer VIA (i.e. a turn in pure metal)
That should warranty that we do not extend a segment in another
metal that may, in turn, cause DRC problem.
* Change: In AutoSegment::revalidate(), disable the check for minimum
area when at least one direct perpandicular is in the same metal
and longer than a half-pitch. This avoid uneeded segments
extensions that may cause DRC violation.
* Change: In AutoSegment::revalidate(), also disable check for minimum
area when in StagePostProcessRoutingPads. We may have reduced
segments to zero-length and don't want them to grow again.
* Change: In AutoSegment, add a new flag IsMergeReducedDone, to avoid
multiple processing of reduced segments while in reduce cluster
stage.
* Change: In Track::repair(), when closing same net gap, add an extra
minSpacing/2 overlap in case the segment would be shrunk by a
post-treatment (leaving small gaps anew).
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