Adding 10BASE-T with direct IO connection

[chmousset]

This PR adds a 10BASE-T PHY which only requires 2 LVDS pairs, 6 resistors and 4 capacitors.
The PHY works in a 40MHz clock domain, both for RX and TX.
It is based on work from https://www.fpga4fun.com/10BASE-T1.html

Current status:

• RX path correctly decodes preamble and data (verified against logic analyzer and Wireshark)
• CRC checker correctly detects errors when
• 👎 when receiving a ping packet, the IP does not answer.

I need some help to debug the higher layers...

To build the SoC:

python bench/arty_multi.py --uart-name uartbone --cpu-type None --csr-csv build/digilent_arty/csr.csv --raw-eth --build --load

[enjoy-digital]

Hi @chmousset,

thanks, interesting. I'm not sure I'll have to time build the hardware but if you can send me the hardware to plug on a Arty board, I would probably be able to allow you to go further in the integration.

[chmousset]

@enjoy-digital sure, I can send you the HW.
I've sent you an email to arrange shipping.

[mithro]

@chmousset - I'm very interested in seeing this work finished! Anything I can do to help?

[enjoy-digital]

@mithro: I received hardware from @chmousset but haven't been able to spent much time on it. I could do more testing in January. If you want to put someone on this, I can also try to provide directions on things I would investigate.