TeamYogaBlade2 · akku1139 · Jan 2, 2026
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -20,6 +20,7 @@ Required properties:
 - compatible: Should be one of:
 	- "mediatek,mt2701-scpsys"
 	- "mediatek,mt2712-scpsys"
+	- "mediatek,mt6589-scpsys"
 	- "mediatek,mt6735-scpsys"
 	- "mediatek,mt6765-scpsys"
 	- "mediatek,mt6797-scpsys"
@@ -36,6 +37,7 @@ Required properties:
                       enabled before enabling certain power domains.
 	Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
 	Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
+	Required clocks for MT6589: "disp", "venc", "vdec"
 	Required clocks for MT6765: MUX: "mm", "mfg"
 				    CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0",
 					"isp-1", "cam-0", "cam-1", "cam-2",

diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi
@@ -101,6 +101,17 @@
 			#reset-cells = <1>;
 		};
 
+		scpsys: power-controller@10006000 {
+			compatible = "mediatek,mt6589-scpsys", "syscon";
+			#power-domain-cells = <1>;
+			reg = <0 0x10006000 0 0x1000>;
+			infracfg = <&infracfg>;
+			clocks = <&topckgen CLK_TOP_MUX_DISP>,
+				 <&topckgen CLK_TOP_MUX_VENC>,
+				 <&topckgen CLK_TOP_MUX_VDEC>;
+			clock-names = "disp", "venc", "vdec";
+		};
+
 		mfgsys: syscon@10206000 {
 			compatible = "mediatek,mt6589-mfgsys", "syscon";
 			reg = <0x10206000 0x1000>;

diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig
@@ -113,6 +113,9 @@ CONFIG_MMC_MTK=y
 ## Reset
 #CONFIG_RESET_CONTROLLER
 
+## Power Management
+CONFIG_MTK_SCPSYS=y
+
 ## Battery
 
 ## Audio

diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/mediatek/mtk-scpsys.c
@@ -15,6 +15,7 @@
 
 #include <dt-bindings/power/mt2701-power.h>
 #include <dt-bindings/power/mt2712-power.h>
+#include <dt-bindings/power/mt6589-power.h>
 #include <dt-bindings/power/mt6797-power.h>
 #include <dt-bindings/power/mt7622-power.h>
 #include <dt-bindings/power/mt7623a-power.h>
@@ -31,8 +32,11 @@
 #define SPM_MFG_PWR_CON			0x0214
 #define SPM_VEN_PWR_CON			0x0230
 #define SPM_ISP_PWR_CON			0x0238
+#define SPM_IFR_PWR_CON			0x0234	/* MT6589 */
 #define SPM_DIS_PWR_CON			0x023c
+#define SPM_DPY_PWR_CON			0x0240	/* MT6589 */
 #define SPM_CONN_PWR_CON		0x0280
+#define SPM_CONN2_PWR_CON		0x0284	/* MT6589 */
 #define SPM_VEN2_PWR_CON		0x0298
 #define SPM_AUDIO_PWR_CON		0x029c	/* MT8173, MT2712 */
 #define SPM_BDP_PWR_CON			0x029c	/* MT2701 */
@@ -58,9 +62,11 @@
 #define PWR_CLK_DIS_BIT			BIT(4)
 
 #define PWR_STATUS_CONN			BIT(1)
+#define PWR_STATUS_DPY			BIT(2)	/* MT6589 */
 #define PWR_STATUS_DISP			BIT(3)
 #define PWR_STATUS_MFG			BIT(4)
 #define PWR_STATUS_ISP			BIT(5)
+#define PWR_STATUS_IFR			BIT(6)	/* MT6589 */
 #define PWR_STATUS_VDEC			BIT(7)
 #define PWR_STATUS_BDP			BIT(14)
 #define PWR_STATUS_ETH			BIT(15)
@@ -89,6 +95,7 @@ enum clk_id {
 	CLK_HIFSEL,
 	CLK_JPGDEC,
 	CLK_AUDIO,
+	CLK_DISP,
 	CLK_MAX,
 };
 
@@ -103,6 +110,7 @@ static const char * const clk_names[] = {
 	"hif_sel",
 	"jpgdec",
 	"audio",
+	"disp",
 	NULL,
 };
 
@@ -748,6 +756,73 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = {
 	{MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
 };
 
+/*
+ * MT6589 power domain support
+ */
+static const struct scp_domain_data scp_domain_data_mt6589[] = {
+	[MT6589_POWER_DOMAIN_MD1] = {
+		.name = "md1",
+		.sta_mask = PWR_STATUS_CONN,
+		.ctl_offs = SPM_CONN2_PWR_CON, /* not miss */
+		.clk_id = {CLK_NONE},
+		.caps = MTK_SCPD_ACTIVE_WAKEUP, /* maybe */
+	},
+	[MT6589_POWER_DOMAIN_MD2] = {
+		.name = "md2",
+		.sta_mask = PWR_STATUS_CONN,
+		.ctl_offs = SPM_CONN_PWR_CON,
+		.clk_id = {CLK_NONE},
+		.caps = MTK_SCPD_ACTIVE_WAKEUP, /* maybe */
+	},
+	[MT6589_POWER_DOMAIN_DPY] = {
+		.name = "dpy",
+		.sta_mask = PWR_STATUS_DPY,
+		.ctl_offs = SPM_DPY_PWR_CON,
+		.clk_id = {CLK_NONE},
+		.caps = MTK_SCPD_ACTIVE_WAKEUP, /* maybe */
+	},
+	[MT6589_POWER_DOMAIN_DIS] = {
+		.name = "disp",
+		.sta_mask = PWR_STATUS_DISP,
+		.ctl_offs = SPM_DIS_PWR_CON,
+		.clk_id = {CLK_DISP},
+	},
+	[MT6589_POWER_DOMAIN_MFG] = {
+		.name = "mfg",
+		.sta_mask = PWR_STATUS_MFG,
+		.ctl_offs = SPM_MFG_PWR_CON,
+		.clk_id = {CLK_NONE},
+	},
+	[MT6589_POWER_DOMAIN_ISP] = {
+		.name = "isp",
+		.sta_mask = PWR_STATUS_ISP,
+		.ctl_offs = SPM_ISP_PWR_CON,
+		.clk_id = {CLK_NONE},
+	},
+	[MT6589_POWER_DOMAIN_IFR] = {
+		.name = "ifr",
+		.sta_mask = PWR_STATUS_IFR,
+		.ctl_offs = SPM_IFR_PWR_CON,
+		.clk_id = {CLK_NONE},
+		.caps = MTK_SCPD_ACTIVE_WAKEUP, /* maybe */
+	},
+	[MT6589_POWER_DOMAIN_VEN] = {
+		.name = "venc",
+		.sta_mask = BIT(7),
+		.ctl_offs = SPM_VEN_PWR_CON,
+		.clk_id = {CLK_VENC},
+	},
+	[MT6589_POWER_DOMAIN_VDE] = {
+		.name = "vdec",
+		.sta_mask = BIT(8),
+		.ctl_offs = SPM_VDE_PWR_CON,
+		.clk_id = {CLK_VDEC},
+	},
+};
+
+static const struct scp_subdomain scp_subdomain_mt6589[] = {
+};
+
 /*
  * MT6797 power domain support
  */
@@ -1031,6 +1106,18 @@ static const struct scp_soc_data mt2712_data = {
 	.bus_prot_reg_update = false,
 };
 
+static const struct scp_soc_data mt6589_data = {
+	.domains = scp_domain_data_mt6589,
+	.num_domains = ARRAY_SIZE(scp_domain_data_mt6589),
+	.subdomains = scp_subdomain_mt6589,
+	.num_subdomains = ARRAY_SIZE(scp_subdomain_mt6589),
+	.regs = {
+//		.pwr_sta_offs = SPM_PWR_STATUS,
+//		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+	},
+//	.bus_prot_reg_update = false,
+};
+
 static const struct scp_soc_data mt6797_data = {
 	.domains = scp_domain_data_mt6797,
 	.num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
@@ -1086,6 +1173,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
 	}, {
 		.compatible = "mediatek,mt2712-scpsys",
 		.data = &mt2712_data,
+	}, {
+		.compatible = "mediatek,mt6589-scpsys",
+		.data = &mt6589_data,
 	}, {
 		.compatible = "mediatek,mt6797-scpsys",
 		.data = &mt6797_data,

diff --git a/include/dt-bindings/power/mt6589-power.h b/include/dt-bindings/power/mt6589-power.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 akku <akkun11.open@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT6589_POWER_H
+#define _DT_BINDINGS_POWER_MT6589_POWER_H
+
+/*
+ * FC0
+ * DBG
+ * CPU
+ * FC1
+ * FC2
+ * FC3
+ * IFR_FH
+ */
+
+#define MT6589_POWER_DOMAIN_MD1	0
+#define MT6589_POWER_DOMAIN_MD2	1
+#define MT6589_POWER_DOMAIN_DPY	2
+#define MT6589_POWER_DOMAIN_DIS	3
+#define MT6589_POWER_DOMAIN_MFG	4
+#define MT6589_POWER_DOMAIN_ISP	5
+#define MT6589_POWER_DOMAIN_IFR	6
+#define MT6589_POWER_DOMAIN_VEN	7
+#define MT6589_POWER_DOMAIN_VDE	8
+
+#endif /* _DT_BINDINGS_POWER_MT6589_POWER_H */