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Update test fixtures and test functions to provide parity_check_group when testing _pauli_axis_cache and _collect_dependent_chain, which are only initialized when parity_check_group is provided (FTQC optimization). 🤖 Generated with [Claude Code](https://claude.com/claude-code) Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
Codecov Report❌ Patch coverage is Additional details and impacted files@@ Coverage Diff @@
## master #132 +/- ##
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+ Coverage 83.57% 83.75% +0.18%
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Files 21 21
Lines 2313 2383 +70
Branches 416 424 +8
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+ Hits 1933 1996 +63
- Misses 288 293 +5
- Partials 92 94 +2 🚀 New features to boost your workflow:
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- Merge scheduling logic into circuit2graph, now returns (GraphState, gflow, Scheduler) - Remove circuit2graph_with_preschedule (unreleased) - Add 9 new tests for scheduling functionality - Update existing tests and examples for new return type 🤖 Generated with [Claude Code](https://claude.com/claude-code) Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
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memo: I have to implement a minimize space pre-schedule |
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I should update the changelog |
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| self._pauli_axis_cache = ( | ||
| {node: determine_pauli_axis(meas_basis) for node, meas_basis in graphstate.meas_bases.items()} | ||
| if parity_check_group | ||
| else {} |
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Because _pauli_axis_cache is now only built when parity_check_group is non-empty, any call to PauliFrame.logical_observables_group() (used by stim_compile when logical_observables is provided) will hit self._pauli_axis_cache[node] and raise a KeyError if parity_check_group was omitted. This makes stim_compile(..., logical_observables=...) crash in the common case where callers don’t provide parity check groups, even though the API doesn’t require them.
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Before submitting, please check the following:
pytest)ruffmypyandpyrightmake htmlin./docs/- you may need to install dependency for sphinx docs, seedocs/requirements.txt.)Then, please fill in below:
Context (if applicable):
For compiling a circuit, the scheduler can be a bottleneck of the process. I found that we can do the optimal schedule (minimizing space/time) during the circuit transpilation.
Description of the change:
I have implemented a new circuit transpiler that gives not only
graphandgflow, but also a schedule based on the given strategy.Also, I have optimized the
GraphStateclass to maximize the compilation speed.