Pinned Loading

1. tt07_cdc_fifo tt07_cdc_fifo Public

   Tapeout of "Clock Domain Crossing FIFO" module using Tinytapeout(tt07) shuttle

   SystemVerilog 2

2. RISC-V_HDP RISC-V_HDP Public

   Design of a Customizable RISC-V SoC for Clapswitch Application

   Verilog 2

3. Current_Starved_VCO_IHP Current_Starved_VCO_IHP Public

   Voltage Controlled Oscillator that produces 1GHz output frequency at voltage 3.3V using IHP PDK as a part of eSim Marathon

4. PLL_130nm PLL_130nm Public

   Circuit Design and Simulation Hackathon using Opensource tools conducted by NIT Jamshedpur and VSD