From 5ffd6c1b7fe123d49ac671257e6ce8feb7b31303 Mon Sep 17 00:00:00 2001 From: Luca Della Vedova Date: Mon, 18 Oct 2021 16:14:37 +0800 Subject: [PATCH 1/3] Update constraints and add smbus IIC Signed-off-by: Luca Della Vedova --- .../constrs_1/new/debug_constraints.xdc | 102 +- .../sources_1/bd/design_1/design_1.bd | 1048 +++++--- .../bd/design_1/hdl/design_1_wrapper.v | 36 +- ovc5/firmware/carrier_board/carrier_board.xpr | 2248 ++++++++++++++++- ovc5/firmware/petalinux/.petalinux/metadata | 4 +- 5 files changed, 2985 insertions(+), 453 deletions(-) diff --git a/ovc5/firmware/carrier_board/carrier_board.srcs/constrs_1/new/debug_constraints.xdc b/ovc5/firmware/carrier_board/carrier_board.srcs/constrs_1/new/debug_constraints.xdc index b4bc05aa..afb58056 100644 --- a/ovc5/firmware/carrier_board/carrier_board.srcs/constrs_1/new/debug_constraints.xdc +++ b/ovc5/firmware/carrier_board/carrier_board.srcs/constrs_1/new/debug_constraints.xdc @@ -4,60 +4,55 @@ set_property DCI_CASCADE {66} [get_iobanks 65] # Trigger pins set_property SLEW SLOW [get_ports {TRIG0[0]}] set_property SLEW SLOW [get_ports {TRIG1[0]}] -set_property PACKAGE_PIN G5 [get_ports {TRIG0[0]}] -set_property IOSTANDARD LVCMOS12 [get_ports {TRIG0[0]}] -set_property PACKAGE_PIN H4 [get_ports {TRIG1[0]}] -set_property IOSTANDARD LVCMOS12 [get_ports {TRIG1[0]}] -set_property PACKAGE_PIN C9 [get_ports {TRIG2[0]}] -set_property IOSTANDARD LVCMOS12 [get_ports {TRIG2[0]}] -set_property PACKAGE_PIN D11 [get_ports {TRIG3[0]}] +set_property PACKAGE_PIN AE10 [get_ports {TRIG0[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TRIG0[0]}] +set_property PACKAGE_PIN AD10 [get_ports {TRIG1[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TRIG1[0]}] +set_property PACKAGE_PIN AH10 [get_ports {TRIG2[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TRIG2[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {TRIG3[0]}] -set_property PACKAGE_PIN B4 [get_ports {TRIG4[0]}] -set_property IOSTANDARD LVCMOS12 [get_ports {TRIG4[0]}] -set_property PACKAGE_PIN T6 [get_ports {TRIG5[0]}] -set_property IOSTANDARD LVCMOS12 [get_ports {TRIG5[0]}] +set_property PACKAGE_PIN AG10 [get_ports {TRIG4[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TRIG4[0]}] +set_property PACKAGE_PIN AD11 [get_ports {TRIG5[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TRIG5[0]}] set_property DRIVE 8 [get_ports {TRIG3[0]}] # Enable pins -set_property PACKAGE_PIN L2 [get_ports {ENABLE[5]}] -set_property PACKAGE_PIN A4 [get_ports {ENABLE[4]}] -set_property PACKAGE_PIN E10 [get_ports {ENABLE[3]}] -set_property PACKAGE_PIN B9 [get_ports {ENABLE[2]}] -set_property PACKAGE_PIN H3 [get_ports {ENABLE[1]}] -set_property PACKAGE_PIN A1 [get_ports {ENABLE[0]}] -set_property IOSTANDARD LVCMOS12 [get_ports {ENABLE[5]}] -set_property IOSTANDARD LVCMOS12 [get_ports {ENABLE[4]}] -set_property IOSTANDARD LVCMOS18 [get_ports {ENABLE[3]}] -set_property IOSTANDARD LVCMOS12 [get_ports {ENABLE[2]}] -set_property IOSTANDARD LVCMOS12 [get_ports {ENABLE[1]}] -set_property IOSTANDARD LVCMOS12 [get_ports {ENABLE[0]}] +set_property PACKAGE_PIN AE15 [get_ports {ENABLE[5]}] +set_property PACKAGE_PIN AE13 [get_ports {ENABLE[4]}] +set_property PACKAGE_PIN AF13 [get_ports {ENABLE[2]}] +set_property PACKAGE_PIN AE14 [get_ports {ENABLE[1]}] +set_property PACKAGE_PIN AH13 [get_ports {ENABLE[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE[0]}] set_property DRIVE 8 [get_ports {ENABLE[3]}] # i2c definitions -set_property PACKAGE_PIN A2 [get_ports iic_rtl_0_scl_io] -set_property PACKAGE_PIN F5 [get_ports iic_rtl_0_sda_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_0_scl_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_0_sda_io] -set_property PACKAGE_PIN H9 [get_ports iic_rtl_1_scl_io] -set_property PACKAGE_PIN H8 [get_ports iic_rtl_1_sda_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_1_scl_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_1_sda_io] -set_property PACKAGE_PIN E9 [get_ports iic_rtl_2_scl_io] -set_property PACKAGE_PIN D9 [get_ports iic_rtl_2_sda_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_2_scl_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_2_sda_io] -set_property PACKAGE_PIN D10 [get_ports iic_rtl_3_scl_io] -set_property PACKAGE_PIN E12 [get_ports iic_rtl_3_sda_io] +set_property PACKAGE_PIN D10 [get_ports iic_rtl_0_sda_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_0_scl_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_0_sda_io] +set_property PACKAGE_PIN Y9 [get_ports iic_rtl_1_scl_io] +set_property PACKAGE_PIN AA8 [get_ports iic_rtl_1_sda_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_1_scl_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_1_sda_io] +set_property PACKAGE_PIN AC12 [get_ports iic_rtl_2_scl_io] +set_property PACKAGE_PIN AD12 [get_ports iic_rtl_2_sda_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_2_scl_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_2_sda_io] set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_3_scl_io] set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_3_sda_io] -set_property PACKAGE_PIN A3 [get_ports iic_rtl_4_scl_io] -set_property PACKAGE_PIN B3 [get_ports iic_rtl_4_sda_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_4_scl_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_4_sda_io] -set_property PACKAGE_PIN R6 [get_ports iic_rtl_5_scl_io] -set_property PACKAGE_PIN L3 [get_ports iic_rtl_5_sda_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_5_scl_io] -set_property IOSTANDARD LVCMOS12 [get_ports iic_rtl_5_sda_io] +set_property PACKAGE_PIN W10 [get_ports iic_rtl_4_scl_io] +set_property PACKAGE_PIN Y10 [get_ports iic_rtl_4_sda_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_4_scl_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_4_sda_io] +set_property PACKAGE_PIN AA11 [get_ports iic_rtl_5_scl_io] +set_property PACKAGE_PIN AA10 [get_ports iic_rtl_5_sda_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_5_scl_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_rtl_5_sda_io] set_property DRIVE 8 [get_ports iic_rtl_0_scl_io] set_property DRIVE 8 [get_ports iic_rtl_0_sda_io] set_property DRIVE 8 [get_ports iic_rtl_1_scl_io] @@ -76,7 +71,7 @@ set_property PACKAGE_PIN AC14 [get_ports {USER_LEDS[0]}] set_property PACKAGE_PIN AC13 [get_ports {USER_LEDS[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {USER_LEDS[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {USER_LEDS[1]}] -set_property PACKAGE_PIN W12 [get_ports USER_DIP] +set_property PACKAGE_PIN W14 [get_ports USER_DIP] set_property IOSTANDARD LVCMOS33 [get_ports USER_DIP] set_property PACKAGE_PIN AH12 [get_ports {GPIO[0]}] set_property PACKAGE_PIN AH11 [get_ports {GPIO[1]}] @@ -92,7 +87,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports {GPIO[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {GPIO[0]}] # i2c headers -set_property PACKAGE_PIN AH14 [get_ports qwiic_rtl_0_scl_io] set_property PACKAGE_PIN AG14 [get_ports qwiic_rtl_0_sda_io] set_property PACKAGE_PIN AB13 [get_ports qwiic_rtl_1_scl_io] set_property PACKAGE_PIN AA13 [get_ports qwiic_rtl_1_sda_io] @@ -111,4 +105,16 @@ set_property IOSTANDARD LVCMOS18 [get_ports {TRIG_PROBE[0]}] set_property PACKAGE_PIN AE12 [get_ports {FRAME_START_0[0]}] set_property PACKAGE_PIN AF12 [get_ports {FRAME_END_0[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {FRAME_END_0[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports {FRAME_START_0[0]}] \ No newline at end of file +set_property IOSTANDARD LVCMOS18 [get_ports {FRAME_START_0[0]}] + +set_property PACKAGE_PIN AH14 [get_ports qwiic_rtl_0_scl_io] +set_property PACKAGE_PIN E10 [get_ports iic_rtl_0_scl_io] +set_property PACKAGE_PIN E12 [get_ports iic_rtl_3_scl_io] +set_property PACKAGE_PIN D11 [get_ports iic_rtl_3_sda_io] +set_property PACKAGE_PIN AG13 [get_ports {ENABLE[3]}] +set_property PACKAGE_PIN AF10 [get_ports {TRIG3[0]}] + +set_property PACKAGE_PIN W12 [get_ports usb_smbus_rtl_0_scl_io] +set_property IOSTANDARD LVCMOS33 [get_ports usb_smbus_rtl_0_scl_io] +set_property PACKAGE_PIN W11 [get_ports usb_smbus_rtl_0_sda_io] +set_property IOSTANDARD LVCMOS33 [get_ports usb_smbus_rtl_0_sda_io] diff --git a/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/design_1.bd b/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/design_1.bd index 3f4d7499..ea676cf8 100644 --- a/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/design_1.bd +++ b/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/design_1.bd @@ -1,7 +1,7 @@ { "design": { "design_info": { - "boundary_crc": "0xAB2623C1F3D2EE1D", + "boundary_crc": "0x25961F728EF1360C", "device": "xczu4ev-sfvc784-1-i", "name": "design_1", "rev_ctrl_bd_flag": "RevCtrlBdOff", @@ -12,6 +12,12 @@ "design_tree": { "ps8_0_axi_periph": { "xbar": "", + "tier2_xbar_0": "", + "tier2_xbar_1": "", + "tier2_xbar_2": "", + "i00_couplers": {}, + "i01_couplers": {}, + "i02_couplers": {}, "s00_couplers": { "auto_pc": "" }, @@ -30,7 +36,8 @@ "m12_couplers": {}, "m13_couplers": {}, "m14_couplers": {}, - "m15_couplers": {} + "m15_couplers": {}, + "m16_couplers": {} }, "rst_ps8_0_100M": "", "zynq_ultra_ps_e_0": "", @@ -93,7 +100,8 @@ "user_i2c": { "qwiic_iic_1": "", "qwiic_iic_2": "", - "qwiic_iic_0": "" + "qwiic_iic_0": "", + "usb_smbus_0": "" }, "Debug": { "fs_inverter": "", @@ -167,6 +175,10 @@ "qwiic_rtl_2": { "mode": "Master", "vlnv": "xilinx.com:interface:iic_rtl:1.0" + }, + "usb_smbus_rtl_0": { + "mode": "Master", + "vlnv": "xilinx.com:interface:iic_rtl:1.0" } }, "ports": { @@ -371,7 +383,7 @@ "value": "0" }, "NUM_MI": { - "value": "16" + "value": "17" } }, "interface_ports": { @@ -442,6 +454,10 @@ "M15_AXI": { "mode": "Master", "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M16_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { @@ -729,6 +745,22 @@ "M15_ARESETN": { "type": "rst", "direction": "I" + }, + "M16_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M16_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M16_ARESETN" + } + } + }, + "M16_ARESETN": { + "type": "rst", + "direction": "I" } }, "components": { @@ -737,7 +769,7 @@ "xci_name": "design_1_xbar_0", "parameters": { "NUM_MI": { - "value": "16" + "value": "3" }, "NUM_SI": { "value": "1" @@ -746,6 +778,28 @@ "value": "0" } }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI" + ] + } + } + }, + "tier2_xbar_0": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_1_tier2_xbar_0_0", + "parameters": { + "NUM_MI": { + "value": "8" + }, + "NUM_SI": { + "value": "1" + } + }, "interface_ports": { "S00_AXI": { "mode": "Slave", @@ -757,15 +811,216 @@ "M04_AXI", "M05_AXI", "M06_AXI", - "M07_AXI", - "M08_AXI", - "M09_AXI", - "M10_AXI", - "M11_AXI", - "M12_AXI", - "M13_AXI", - "M14_AXI", - "M15_AXI" + "M07_AXI" + ] + } + } + }, + "tier2_xbar_1": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_1_tier2_xbar_1_0", + "parameters": { + "NUM_MI": { + "value": "7" + }, + "NUM_SI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI", + "M03_AXI", + "M04_AXI", + "M05_AXI", + "M06_AXI" + ] + } + } + }, + "tier2_xbar_2": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "design_1_tier2_xbar_2_0", + "parameters": { + "NUM_MI": { + "value": "2" + }, + "NUM_SI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI" + ] + } + } + }, + "i00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "i00_couplers_to_i00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "i01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "i01_couplers_to_i01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "i02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "i02_couplers_to_i02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" ] } } @@ -1398,7 +1653,61 @@ } }, "interface_nets": { - "m09_couplers_to_m09_couplers": { + "m09_couplers_to_m09_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m10_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m10_couplers_to_m10_couplers": { "interface_ports": [ "S_AXI", "M_AXI" @@ -1406,7 +1715,7 @@ } } }, - "m10_couplers": { + "m11_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", @@ -1452,7 +1761,7 @@ } }, "interface_nets": { - "m10_couplers_to_m10_couplers": { + "m11_couplers_to_m11_couplers": { "interface_ports": [ "S_AXI", "M_AXI" @@ -1460,7 +1769,7 @@ } } }, - "m11_couplers": { + "m12_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", @@ -1506,7 +1815,7 @@ } }, "interface_nets": { - "m11_couplers_to_m11_couplers": { + "m12_couplers_to_m12_couplers": { "interface_ports": [ "S_AXI", "M_AXI" @@ -1514,7 +1823,7 @@ } } }, - "m12_couplers": { + "m13_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", @@ -1560,7 +1869,7 @@ } }, "interface_nets": { - "m12_couplers_to_m12_couplers": { + "m13_couplers_to_m13_couplers": { "interface_ports": [ "S_AXI", "M_AXI" @@ -1568,7 +1877,7 @@ } } }, - "m13_couplers": { + "m14_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", @@ -1614,7 +1923,7 @@ } }, "interface_nets": { - "m13_couplers_to_m13_couplers": { + "m14_couplers_to_m14_couplers": { "interface_ports": [ "S_AXI", "M_AXI" @@ -1622,7 +1931,7 @@ } } }, - "m14_couplers": { + "m15_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", @@ -1668,7 +1977,7 @@ } }, "interface_nets": { - "m14_couplers_to_m14_couplers": { + "m15_couplers_to_m15_couplers": { "interface_ports": [ "S_AXI", "M_AXI" @@ -1676,7 +1985,7 @@ } } }, - "m15_couplers": { + "m16_couplers": { "interface_ports": { "M_AXI": { "mode": "Master", @@ -1722,7 +2031,7 @@ } }, "interface_nets": { - "m15_couplers_to_m15_couplers": { + "m16_couplers_to_m16_couplers": { "interface_ports": [ "S_AXI", "M_AXI" @@ -1732,34 +2041,40 @@ } }, "interface_nets": { - "xbar_to_m05_couplers": { + "m08_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "xbar/M05_AXI", - "m05_couplers/S_AXI" + "M08_AXI", + "m08_couplers/M_AXI" ] }, - "xbar_to_m01_couplers": { + "tier2_xbar_0_to_m07_couplers": { "interface_ports": [ - "xbar/M01_AXI", - "m01_couplers/S_AXI" + "tier2_xbar_0/M07_AXI", + "m07_couplers/S_AXI" ] }, - "m12_couplers_to_ps8_0_axi_periph": { + "m09_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "M12_AXI", - "m12_couplers/M_AXI" + "M09_AXI", + "m09_couplers/M_AXI" ] }, - "m08_couplers_to_ps8_0_axi_periph": { + "tier2_xbar_1_to_m08_couplers": { "interface_ports": [ - "M08_AXI", - "m08_couplers/M_AXI" + "tier2_xbar_1/M00_AXI", + "m08_couplers/S_AXI" ] }, - "m09_couplers_to_ps8_0_axi_periph": { + "m10_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "M09_AXI", - "m09_couplers/M_AXI" + "M10_AXI", + "m10_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m09_couplers": { + "interface_ports": [ + "tier2_xbar_1/M01_AXI", + "m09_couplers/S_AXI" ] }, "m13_couplers_to_ps8_0_axi_periph": { @@ -1768,34 +2083,58 @@ "m13_couplers/M_AXI" ] }, - "m10_couplers_to_ps8_0_axi_periph": { + "tier2_xbar_1_to_m12_couplers": { "interface_ports": [ - "M10_AXI", - "m10_couplers/M_AXI" + "tier2_xbar_1/M04_AXI", + "m12_couplers/S_AXI" ] }, - "xbar_to_m12_couplers": { + "m14_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "xbar/M12_AXI", - "m12_couplers/S_AXI" + "M14_AXI", + "m14_couplers/M_AXI" ] }, - "m15_couplers_to_ps8_0_axi_periph": { + "tier2_xbar_1_to_m13_couplers": { "interface_ports": [ - "M15_AXI", - "m15_couplers/M_AXI" + "tier2_xbar_1/M05_AXI", + "m13_couplers/S_AXI" ] }, - "m11_couplers_to_ps8_0_axi_periph": { + "m12_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "M11_AXI", - "m11_couplers/M_AXI" + "M12_AXI", + "m12_couplers/M_AXI" ] }, - "xbar_to_m03_couplers": { + "tier2_xbar_1_to_m11_couplers": { "interface_ports": [ - "xbar/M03_AXI", - "m03_couplers/S_AXI" + "tier2_xbar_1/M03_AXI", + "m11_couplers/S_AXI" + ] + }, + "ps8_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "tier2_xbar_2_to_m16_couplers": { + "interface_ports": [ + "tier2_xbar_2/M01_AXI", + "m16_couplers/S_AXI" + ] + }, + "tier2_xbar_2_to_m15_couplers": { + "interface_ports": [ + "tier2_xbar_2/M00_AXI", + "m15_couplers/S_AXI" + ] + }, + "m16_couplers_to_ps8_0_axi_periph": { + "interface_ports": [ + "M16_AXI", + "m16_couplers/M_AXI" ] }, "m06_couplers_to_ps8_0_axi_periph": { @@ -1804,22 +2143,28 @@ "m06_couplers/M_AXI" ] }, - "xbar_to_m00_couplers": { + "tier2_xbar_0_to_m06_couplers": { "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" + "tier2_xbar_0/M06_AXI", + "m06_couplers/S_AXI" ] }, - "xbar_to_m08_couplers": { + "m07_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "xbar/M08_AXI", - "m08_couplers/S_AXI" + "M07_AXI", + "m07_couplers/M_AXI" ] }, - "m03_couplers_to_ps8_0_axi_periph": { + "m15_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "M03_AXI", - "m03_couplers/M_AXI" + "M15_AXI", + "m15_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m14_couplers": { + "interface_ports": [ + "tier2_xbar_1/M06_AXI", + "m14_couplers/S_AXI" ] }, "s00_couplers_to_xbar": { @@ -1828,58 +2173,70 @@ "xbar/S00_AXI" ] }, + "m11_couplers_to_ps8_0_axi_periph": { + "interface_ports": [ + "M11_AXI", + "m11_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m10_couplers": { + "interface_ports": [ + "tier2_xbar_1/M02_AXI", + "m10_couplers/S_AXI" + ] + }, "m00_couplers_to_ps8_0_axi_periph": { "interface_ports": [ "M00_AXI", "m00_couplers/M_AXI" ] }, - "m02_couplers_to_ps8_0_axi_periph": { + "i00_couplers_to_tier2_xbar_0": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "i00_couplers/M_AXI", + "tier2_xbar_0/S00_AXI" ] }, - "xbar_to_m02_couplers": { + "xbar_to_i02_couplers": { "interface_ports": [ "xbar/M02_AXI", - "m02_couplers/S_AXI" + "i02_couplers/S_AXI" ] }, - "xbar_to_m13_couplers": { + "m05_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "xbar/M13_AXI", - "m13_couplers/S_AXI" + "M05_AXI", + "m05_couplers/M_AXI" ] }, - "xbar_to_m09_couplers": { + "tier2_xbar_0_to_m04_couplers": { "interface_ports": [ - "xbar/M09_AXI", - "m09_couplers/S_AXI" + "tier2_xbar_0/M04_AXI", + "m04_couplers/S_AXI" ] }, - "xbar_to_m11_couplers": { + "tier2_xbar_0_to_m05_couplers": { "interface_ports": [ - "xbar/M11_AXI", - "m11_couplers/S_AXI" + "tier2_xbar_0/M05_AXI", + "m05_couplers/S_AXI" ] }, - "xbar_to_m10_couplers": { + "tier2_xbar_0_to_m03_couplers": { "interface_ports": [ - "xbar/M10_AXI", - "m10_couplers/S_AXI" + "tier2_xbar_0/M03_AXI", + "m03_couplers/S_AXI" ] }, - "m14_couplers_to_ps8_0_axi_periph": { + "m04_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "M14_AXI", - "m14_couplers/M_AXI" + "M04_AXI", + "m04_couplers/M_AXI" ] }, - "xbar_to_m14_couplers": { + "i02_couplers_to_tier2_xbar_2": { "interface_ports": [ - "xbar/M14_AXI", - "m14_couplers/S_AXI" + "i02_couplers/M_AXI", + "tier2_xbar_2/S00_AXI" ] }, "m01_couplers_to_ps8_0_axi_periph": { @@ -1888,52 +2245,52 @@ "m01_couplers/M_AXI" ] }, - "xbar_to_m06_couplers": { + "tier2_xbar_0_to_m02_couplers": { "interface_ports": [ - "xbar/M06_AXI", - "m06_couplers/S_AXI" + "tier2_xbar_0/M02_AXI", + "m02_couplers/S_AXI" ] }, - "m07_couplers_to_ps8_0_axi_periph": { + "tier2_xbar_0_to_m00_couplers": { "interface_ports": [ - "M07_AXI", - "m07_couplers/M_AXI" + "tier2_xbar_0/M00_AXI", + "m00_couplers/S_AXI" ] }, - "m05_couplers_to_ps8_0_axi_periph": { + "m03_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "M05_AXI", - "m05_couplers/M_AXI" + "M03_AXI", + "m03_couplers/M_AXI" ] }, - "ps8_0_axi_periph_to_s00_couplers": { + "tier2_xbar_0_to_m01_couplers": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "tier2_xbar_0/M01_AXI", + "m01_couplers/S_AXI" ] }, - "xbar_to_m04_couplers": { + "m02_couplers_to_ps8_0_axi_periph": { "interface_ports": [ - "xbar/M04_AXI", - "m04_couplers/S_AXI" + "M02_AXI", + "m02_couplers/M_AXI" ] }, - "xbar_to_m07_couplers": { + "i01_couplers_to_tier2_xbar_1": { "interface_ports": [ - "xbar/M07_AXI", - "m07_couplers/S_AXI" + "i01_couplers/M_AXI", + "tier2_xbar_1/S00_AXI" ] }, - "xbar_to_m15_couplers": { + "xbar_to_i00_couplers": { "interface_ports": [ - "xbar/M15_AXI", - "m15_couplers/S_AXI" + "xbar/M00_AXI", + "i00_couplers/S_AXI" ] }, - "m04_couplers_to_ps8_0_axi_periph": { + "xbar_to_i01_couplers": { "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" + "xbar/M01_AXI", + "i01_couplers/S_AXI" ] } }, @@ -1942,6 +2299,15 @@ "ports": [ "ACLK", "xbar/aclk", + "tier2_xbar_0/aclk", + "tier2_xbar_1/aclk", + "tier2_xbar_2/aclk", + "i00_couplers/S_ACLK", + "i00_couplers/M_ACLK", + "i01_couplers/S_ACLK", + "i01_couplers/M_ACLK", + "i02_couplers/S_ACLK", + "i02_couplers/M_ACLK", "s00_couplers/S_ACLK", "s00_couplers/M_ACLK", "m00_couplers/M_ACLK", @@ -1960,6 +2326,7 @@ "m13_couplers/M_ACLK", "m14_couplers/M_ACLK", "m15_couplers/M_ACLK", + "m16_couplers/M_ACLK", "m00_couplers/S_ACLK", "m01_couplers/S_ACLK", "m02_couplers/S_ACLK", @@ -1975,13 +2342,23 @@ "m12_couplers/S_ACLK", "m13_couplers/S_ACLK", "m14_couplers/S_ACLK", - "m15_couplers/S_ACLK" + "m15_couplers/S_ACLK", + "m16_couplers/S_ACLK" ] }, "ps8_0_axi_periph_ARESETN_net": { "ports": [ "ARESETN", "xbar/aresetn", + "tier2_xbar_0/aresetn", + "tier2_xbar_1/aresetn", + "tier2_xbar_2/aresetn", + "i00_couplers/S_ARESETN", + "i00_couplers/M_ARESETN", + "i01_couplers/S_ARESETN", + "i01_couplers/M_ARESETN", + "i02_couplers/S_ARESETN", + "i02_couplers/M_ARESETN", "s00_couplers/S_ARESETN", "s00_couplers/M_ARESETN", "m00_couplers/M_ARESETN", @@ -2000,6 +2377,7 @@ "m13_couplers/M_ARESETN", "m14_couplers/M_ARESETN", "m15_couplers/M_ARESETN", + "m16_couplers/M_ARESETN", "m00_couplers/S_ARESETN", "m01_couplers/S_ARESETN", "m02_couplers/S_ARESETN", @@ -2015,7 +2393,8 @@ "m12_couplers/S_ARESETN", "m13_couplers/S_ARESETN", "m14_couplers/S_ARESETN", - "m15_couplers/S_ARESETN" + "m15_couplers/S_ARESETN", + "m16_couplers/S_ARESETN" ] } } @@ -5033,7 +5412,7 @@ "components": { "gpio_trigger_slice": { "vlnv": "xilinx.com:ip:xlslice:1.0", - "xci_name": "design_1_gpio_i_slice_1", + "xci_name": "design_1_gpio_trigger_slice_0", "parameters": { "DIN_FROM": { "value": "15" @@ -5495,7 +5874,7 @@ "components": { "mipi_csi2_rx_subsystem": { "vlnv": "xilinx.com:ip:mipi_csi2_rx_subsystem:5.1", - "xci_name": "design_1_mipi_csi2_rx_subsyst_0_0", + "xci_name": "design_1_mipi_csi2_rx_subsystem_0", "parameters": { "AXIS_TDATA_WIDTH": { "value": "32" @@ -5586,7 +5965,7 @@ }, "axi_vdma": { "vlnv": "xilinx.com:ip:axi_vdma:6.3", - "xci_name": "design_1_axi_vdma_0_0", + "xci_name": "design_1_axi_vdma_0", "parameters": { "c_include_mm2s": { "value": "0" @@ -5623,7 +6002,7 @@ }, "parameters": { "master_id": { - "value": "1" + "value": "2" } } } @@ -5631,7 +6010,7 @@ }, "iic": { "vlnv": "xilinx.com:ip:axi_iic:2.0", - "xci_name": "design_1_cam_iic_1_0" + "xci_name": "design_1_iic_0" } }, "interface_nets": { @@ -5827,7 +6206,7 @@ "components": { "mipi_csi2_rx_subsystem": { "vlnv": "xilinx.com:ip:mipi_csi2_rx_subsystem:5.1", - "xci_name": "design_1_mipi_csi2_rx_subsyst_5_0", + "xci_name": "design_1_mipi_csi2_rx_subsystem_1", "parameters": { "AXIS_TDATA_WIDTH": { "value": "32" @@ -5909,7 +6288,7 @@ }, "axi_vdma": { "vlnv": "xilinx.com:ip:axi_vdma:6.3", - "xci_name": "design_1_axi_vdma_5_0", + "xci_name": "design_1_axi_vdma_1", "parameters": { "c_include_mm2s": { "value": "0" @@ -5946,7 +6325,7 @@ }, "parameters": { "master_id": { - "value": "2" + "value": "5" } } } @@ -5954,16 +6333,10 @@ }, "iic": { "vlnv": "xilinx.com:ip:axi_iic:2.0", - "xci_name": "design_1_cam_iic_5_0" + "xci_name": "design_1_iic_1" } }, "interface_nets": { - "ps8_0_axi_periph_M15_AXI": { - "interface_ports": [ - "S_AXI_LITE", - "axi_vdma/S_AXI_LITE" - ] - }, "ps8_0_axi_periph_M08_AXI": { "interface_ports": [ "S_AXI1", @@ -5993,6 +6366,12 @@ "mipi_csi2_rx_subsystem/video_out", "axi_vdma/S_AXIS_S2MM" ] + }, + "ps8_0_axi_periph_M15_AXI": { + "interface_ports": [ + "S_AXI_LITE", + "axi_vdma/S_AXI_LITE" + ] } }, "nets": { @@ -6150,7 +6529,7 @@ "components": { "mipi_csi2_rx_subsystem": { "vlnv": "xilinx.com:ip:mipi_csi2_rx_subsystem:5.1", - "xci_name": "design_1_mipi_csi2_rx_subsyst_2_0", + "xci_name": "design_1_mipi_csi2_rx_subsystem_2", "parameters": { "AXIS_TDATA_WIDTH": { "value": "32" @@ -6241,7 +6620,7 @@ }, "axi_vdma": { "vlnv": "xilinx.com:ip:axi_vdma:6.3", - "xci_name": "design_1_axi_vdma_2_0", + "xci_name": "design_1_axi_vdma_2", "parameters": { "c_include_mm2s": { "value": "0" @@ -6286,22 +6665,10 @@ }, "iic": { "vlnv": "xilinx.com:ip:axi_iic:2.0", - "xci_name": "design_1_cam_iic_2_0" + "xci_name": "design_1_iic_2" } }, "interface_nets": { - "mipi_csi2_rx_subsystem_video_out": { - "interface_ports": [ - "mipi_csi2_rx_subsystem/video_out", - "axi_vdma/S_AXIS_S2MM" - ] - }, - "Conn1": { - "interface_ports": [ - "S_AXI", - "iic/S_AXI" - ] - }, "axi_vdma_2_M_AXI_S2MM1": { "interface_ports": [ "M_AXI_S2MM", @@ -6325,6 +6692,18 @@ "mipi_phy_if_2", "mipi_csi2_rx_subsystem/mipi_phy_if" ] + }, + "mipi_csi2_rx_subsystem_video_out": { + "interface_ports": [ + "mipi_csi2_rx_subsystem/video_out", + "axi_vdma/S_AXIS_S2MM" + ] + }, + "Conn1": { + "interface_ports": [ + "S_AXI", + "iic/S_AXI" + ] } }, "nets": { @@ -6480,7 +6859,7 @@ "components": { "mipi_csi2_rx_subsystem": { "vlnv": "xilinx.com:ip:mipi_csi2_rx_subsystem:5.1", - "xci_name": "design_1_mipi_csi2_rx_subsyst_3_0", + "xci_name": "design_1_mipi_csi2_rx_subsystem_3", "parameters": { "AXIS_TDATA_WIDTH": { "value": "32" @@ -6571,7 +6950,7 @@ }, "axi_vdma": { "vlnv": "xilinx.com:ip:axi_vdma:6.3", - "xci_name": "design_1_axi_vdma_3_0", + "xci_name": "design_1_axi_vdma_3", "parameters": { "c_include_mm2s": { "value": "0" @@ -6608,7 +6987,7 @@ }, "parameters": { "master_id": { - "value": "4" + "value": "6" } } } @@ -6616,16 +6995,10 @@ }, "iic": { "vlnv": "xilinx.com:ip:axi_iic:2.0", - "xci_name": "design_1_cam_iic_3_0" + "xci_name": "design_1_iic_3" } }, "interface_nets": { - "ps8_0_axi_periph_M13_AXI": { - "interface_ports": [ - "S_AXI_LITE", - "axi_vdma/S_AXI_LITE" - ] - }, "axi_vdma_3_M_AXI_S2MM": { "interface_ports": [ "M_AXI_S2MM", @@ -6655,6 +7028,12 @@ "iic_rtl_3", "iic/IIC" ] + }, + "ps8_0_axi_periph_M13_AXI": { + "interface_ports": [ + "S_AXI_LITE", + "axi_vdma/S_AXI_LITE" + ] } }, "nets": { @@ -6800,11 +7179,11 @@ "components": { "iic": { "vlnv": "xilinx.com:ip:axi_iic:2.0", - "xci_name": "design_1_cam_iic_4_0" + "xci_name": "design_1_iic_4" }, "mipi_csi2_rx_subsystem": { "vlnv": "xilinx.com:ip:mipi_csi2_rx_subsystem:5.1", - "xci_name": "design_1_mipi_csi2_rx_subsyst_4_0", + "xci_name": "design_1_mipi_csi2_rx_subsystem_4", "parameters": { "AXIS_TDATA_WIDTH": { "value": "32" @@ -6886,7 +7265,7 @@ }, "axi_vdma": { "vlnv": "xilinx.com:ip:axi_vdma:6.3", - "xci_name": "design_1_axi_vdma_4_0", + "xci_name": "design_1_axi_vdma_4", "parameters": { "c_include_mm2s": { "value": "0" @@ -6926,7 +7305,7 @@ }, "parameters": { "master_id": { - "value": "5" + "value": "4" } } } @@ -6934,22 +7313,16 @@ } }, "interface_nets": { - "axi_vdma_4_M_AXI_S2MM": { - "interface_ports": [ - "M_AXI_S2MM", - "axi_vdma/M_AXI_S2MM" - ] - }, - "ps8_0_axi_periph_M07_AXI": { + "mipi_phy_if_4_1": { "interface_ports": [ - "S_AXI1", - "iic/S_AXI" + "mipi_phy_if_4", + "mipi_csi2_rx_subsystem/mipi_phy_if" ] }, - "axi_iic_3_IIC": { + "mipi_csi2_rx_subsystem_video_out": { "interface_ports": [ - "iic_rtl_4", - "iic/IIC" + "mipi_csi2_rx_subsystem/video_out", + "axi_vdma/S_AXIS_S2MM" ] }, "ps8_0_axi_periph_M14_AXI": { @@ -6958,16 +7331,22 @@ "axi_vdma/S_AXI_LITE" ] }, - "mipi_phy_if_4_1": { + "axi_iic_3_IIC": { "interface_ports": [ - "mipi_phy_if_4", - "mipi_csi2_rx_subsystem/mipi_phy_if" + "iic_rtl_4", + "iic/IIC" ] }, - "mipi_csi2_rx_subsystem_video_out": { + "ps8_0_axi_periph_M07_AXI": { "interface_ports": [ - "mipi_csi2_rx_subsystem/video_out", - "axi_vdma/S_AXIS_S2MM" + "S_AXI1", + "iic/S_AXI" + ] + }, + "axi_vdma_4_M_AXI_S2MM": { + "interface_ports": [ + "M_AXI_S2MM", + "axi_vdma/M_AXI_S2MM" ] } }, @@ -7119,7 +7498,7 @@ "components": { "mipi_csi2_rx_subsystem": { "vlnv": "xilinx.com:ip:mipi_csi2_rx_subsystem:5.1", - "xci_name": "design_1_mipi_csi2_rx_subsyst_1_0", + "xci_name": "design_1_mipi_csi2_rx_subsystem_5", "parameters": { "AXIS_TDATA_WIDTH": { "value": "32" @@ -7216,7 +7595,7 @@ }, "axi_vdma": { "vlnv": "xilinx.com:ip:axi_vdma:6.3", - "xci_name": "design_1_axi_vdma_1_0", + "xci_name": "design_1_axi_vdma_5", "parameters": { "c_include_mm2s": { "value": "0" @@ -7253,7 +7632,7 @@ }, "parameters": { "master_id": { - "value": "6" + "value": "1" } } } @@ -7261,16 +7640,10 @@ } }, "interface_nets": { - "mipi_csi2_rx_subsyst_0_video_out": { - "interface_ports": [ - "mipi_csi2_rx_subsystem/video_out", - "axi_vdma/S_AXIS_S2MM" - ] - }, - "Conn2": { + "Conn3": { "interface_ports": [ - "mipi_phy_if_0", - "mipi_csi2_rx_subsystem/mipi_phy_if" + "S_AXI_LITE", + "axi_vdma/S_AXI_LITE" ] }, "Conn1": { @@ -7279,10 +7652,16 @@ "axi_vdma/M_AXI_S2MM" ] }, - "Conn3": { + "Conn2": { "interface_ports": [ - "S_AXI_LITE", - "axi_vdma/S_AXI_LITE" + "mipi_phy_if_0", + "mipi_csi2_rx_subsystem/mipi_phy_if" + ] + }, + "mipi_csi2_rx_subsyst_0_video_out": { + "interface_ports": [ + "mipi_csi2_rx_subsystem/video_out", + "axi_vdma/S_AXIS_S2MM" ] } }, @@ -7609,7 +7988,7 @@ }, "selector": { "vlnv": "xilinx.com:ip:util_vector_logic:2.0", - "xci_name": "design_1_util_vector_logic_0_1", + "xci_name": "design_1_selector_0", "parameters": { "C_SIZE": { "value": "6" @@ -7630,7 +8009,7 @@ }, "line_end_inverter": { "vlnv": "xilinx.com:ip:util_vector_logic:2.0", - "xci_name": "design_1_line_end_inverter_6", + "xci_name": "design_1_line_end_inverter_0", "parameters": { "C_OPERATION": { "value": "not" @@ -7642,7 +8021,7 @@ }, "end_line_concat": { "vlnv": "xilinx.com:ip:xlconcat:2.1", - "xci_name": "design_1_line_counter_concat_0", + "xci_name": "design_1_end_line_concat_0", "parameters": { "NUM_PORTS": { "value": "6" @@ -7654,7 +8033,7 @@ }, "line_counter_select": { "vlnv": "xilinx.com:ip:xlslice:1.0", - "xci_name": "design_1_cam_enable_slice_1", + "xci_name": "design_1_line_counter_select_0", "parameters": { "DIN_FROM": { "value": "21" @@ -7672,80 +8051,32 @@ }, "trigger_timer": { "vlnv": "xilinx.com:ip:axi_timer:2.0", - "xci_name": "design_1_trigger_timer_0_0" + "xci_name": "design_1_trigger_timer_0" } }, "interface_nets": { - "mipi_phy_if_4_1": { - "interface_ports": [ - "mipi_phy_if_4", - "cam4/mipi_phy_if_4" - ] - }, - "ps8_0_axi_periph_M14_AXI": { - "interface_ports": [ - "S_AXI_LITE4", - "cam4/S_AXI_LITE" - ] - }, - "cam2_mipi_block_two_lane_iic_rtl_2": { - "interface_ports": [ - "iic_rtl_2", - "cam2/iic_rtl_2" - ] - }, - "ps8_0_axi_periph_M01_AXI": { - "interface_ports": [ - "S_AXI_LITE", - "cam1/S_AXI_LITE" - ] - }, - "mipi_phy_if_1_1": { - "interface_ports": [ - "mipi_phy_if_1", - "cam1/mipi_phy_if_1" - ] - }, - "Conn4": { - "interface_ports": [ - "S_AXI", - "line_counter/S_AXI" - ] - }, - "mipi_phy_if_0_1": { - "interface_ports": [ - "mipi_phy_if_0", - "cam0/mipi_phy_if_0" - ] - }, - "cam2_mipi_block_two_lane_M_AXI_S2MM": { - "interface_ports": [ - "cam2/M_AXI_S2MM", - "axi_smc_1/S00_AXI" - ] - }, - "ps8_0_axi_periph_M00_AXI": { + "ps8_0_axi_periph_M06_AXI": { "interface_ports": [ - "S_AXI_LITE5", - "cam0/S_AXI_LITE" + "S_AXI10", + "cam3/S_AXI1" ] }, - "cam1_mipi_block_four_lane_M_AXI_S2MM": { + "ps8_0_axi_periph_M07_AXI": { "interface_ports": [ - "cam1/M_AXI_S2MM", - "axi_smc/S01_AXI" + "S_AXI12", + "cam4/S_AXI1" ] }, - "ps8_0_axi_periph_M13_AXI": { + "Conn3": { "interface_ports": [ - "S_AXI_LITE3", - "cam3/S_AXI_LITE" + "iic_rtl_3", + "cam3/iic_rtl_3" ] }, - "ps8_0_axi_periph_M05_AXI": { + "ps8_0_axi_periph_M12_AXI": { "interface_ports": [ - "S_AXI8", - "cam2/S_AXI" + "S_AXI_LITE2", + "cam2/S_AXI_LITE" ] }, "axi_iic_3_IIC": { @@ -7772,12 +8103,6 @@ "axi_smc_1/S02_AXI" ] }, - "ps8_0_axi_periph_M08_AXI": { - "interface_ports": [ - "S_AXI6", - "cam5/S_AXI1" - ] - }, "axi_iic_4_IIC": { "interface_ports": [ "iic_rtl_5", @@ -7844,28 +8169,82 @@ "trigger_timer/S_AXI" ] }, - "ps8_0_axi_periph_M06_AXI": { + "mipi_phy_if_0_1": { "interface_ports": [ - "S_AXI10", - "cam3/S_AXI1" + "mipi_phy_if_0", + "cam0/mipi_phy_if_0" ] }, - "ps8_0_axi_periph_M07_AXI": { + "cam2_mipi_block_two_lane_M_AXI_S2MM": { "interface_ports": [ - "S_AXI12", - "cam4/S_AXI1" + "cam2/M_AXI_S2MM", + "axi_smc_1/S00_AXI" ] }, - "Conn3": { + "ps8_0_axi_periph_M00_AXI": { "interface_ports": [ - "iic_rtl_3", - "cam3/iic_rtl_3" + "S_AXI_LITE5", + "cam0/S_AXI_LITE" ] }, - "ps8_0_axi_periph_M12_AXI": { + "cam1_mipi_block_four_lane_M_AXI_S2MM": { "interface_ports": [ - "S_AXI_LITE2", - "cam2/S_AXI_LITE" + "cam1/M_AXI_S2MM", + "axi_smc/S01_AXI" + ] + }, + "ps8_0_axi_periph_M13_AXI": { + "interface_ports": [ + "S_AXI_LITE3", + "cam3/S_AXI_LITE" + ] + }, + "ps8_0_axi_periph_M05_AXI": { + "interface_ports": [ + "S_AXI8", + "cam2/S_AXI" + ] + }, + "Conn4": { + "interface_ports": [ + "S_AXI", + "line_counter/S_AXI" + ] + }, + "mipi_phy_if_1_1": { + "interface_ports": [ + "mipi_phy_if_1", + "cam1/mipi_phy_if_1" + ] + }, + "ps8_0_axi_periph_M01_AXI": { + "interface_ports": [ + "S_AXI_LITE", + "cam1/S_AXI_LITE" + ] + }, + "cam2_mipi_block_two_lane_iic_rtl_2": { + "interface_ports": [ + "iic_rtl_2", + "cam2/iic_rtl_2" + ] + }, + "ps8_0_axi_periph_M14_AXI": { + "interface_ports": [ + "S_AXI_LITE4", + "cam4/S_AXI_LITE" + ] + }, + "mipi_phy_if_4_1": { + "interface_ports": [ + "mipi_phy_if_4", + "cam4/mipi_phy_if_4" + ] + }, + "ps8_0_axi_periph_M08_AXI": { + "interface_ports": [ + "S_AXI6", + "cam5/S_AXI1" ] } }, @@ -8216,12 +8595,16 @@ "In0": { "type": "intr", "direction": "I" + }, + "In15": { + "type": "intr", + "direction": "I" } }, "components": { "irq0_concat": { "vlnv": "xilinx.com:ip:xlconcat:2.1", - "xci_name": "design_1_xlconcat_1_1", + "xci_name": "design_1_irq0_concat_0", "parameters": { "NUM_PORTS": { "value": "8" @@ -8233,7 +8616,7 @@ }, "irq1_concat": { "vlnv": "xilinx.com:ip:xlconcat:2.1", - "xci_name": "design_1_xlconcat_1_0", + "xci_name": "design_1_irq1_concat_0", "parameters": { "NUM_PORTS": { "value": "8" @@ -8346,6 +8729,12 @@ "In0", "irq0_concat/In0" ] + }, + "In15_1": { + "ports": [ + "In15", + "irq1_concat/In7" + ] } } }, @@ -8374,6 +8763,14 @@ "qwiic_rtl_0": { "mode": "Master", "vlnv": "xilinx.com:interface:iic_rtl:1.0" + }, + "IIC_0": { + "mode": "Master", + "vlnv": "xilinx.com:interface:iic_rtl:1.0" + }, + "S_AXI3": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" } }, "ports": { @@ -8396,6 +8793,10 @@ "iic2intc_irpt2": { "type": "intr", "direction": "O" + }, + "iic2intc_irpt3": { + "type": "intr", + "direction": "O" } }, "components": { @@ -8410,9 +8811,25 @@ "qwiic_iic_0": { "vlnv": "xilinx.com:ip:axi_iic:2.0", "xci_name": "design_1_qwiic_iic_0_0" + }, + "usb_smbus_0": { + "vlnv": "xilinx.com:ip:axi_iic:2.0", + "xci_name": "design_1_axi_iic_0_0" } }, "interface_nets": { + "ps8_0_axi_periph_M09_AXI": { + "interface_ports": [ + "S_AXI2", + "qwiic_iic_0/S_AXI" + ] + }, + "qwiic_iic_2_IIC": { + "interface_ports": [ + "qwiic_rtl_2", + "qwiic_iic_2/IIC" + ] + }, "qwiic_iic_1_IIC": { "interface_ports": [ "qwiic_rtl_1", @@ -8437,16 +8854,16 @@ "qwiic_iic_2/S_AXI" ] }, - "ps8_0_axi_periph_M09_AXI": { + "Conn2": { "interface_ports": [ - "S_AXI2", - "qwiic_iic_0/S_AXI" + "S_AXI3", + "usb_smbus_0/S_AXI" ] }, - "qwiic_iic_2_IIC": { + "Conn1": { "interface_ports": [ - "qwiic_rtl_2", - "qwiic_iic_2/IIC" + "IIC_0", + "usb_smbus_0/IIC" ] } }, @@ -8456,7 +8873,8 @@ "s_axi_aclk", "qwiic_iic_0/s_axi_aclk", "qwiic_iic_2/s_axi_aclk", - "qwiic_iic_1/s_axi_aclk" + "qwiic_iic_1/s_axi_aclk", + "usb_smbus_0/s_axi_aclk" ] }, "rst_ps8_0_49M_peripheral_aresetn": { @@ -8464,7 +8882,8 @@ "s_axi_aresetn", "qwiic_iic_0/s_axi_aresetn", "qwiic_iic_2/s_axi_aresetn", - "qwiic_iic_1/s_axi_aresetn" + "qwiic_iic_1/s_axi_aresetn", + "usb_smbus_0/s_axi_aresetn" ] }, "qwiic_iic_1_iic2intc_irpt": { @@ -8484,6 +8903,12 @@ "qwiic_iic_0/iic2intc_irpt", "iic2intc_irpt2" ] + }, + "usb_smbus_0_iic2intc_irpt": { + "ports": [ + "usb_smbus_0/iic2intc_irpt", + "iic2intc_irpt3" + ] } } }, @@ -8794,10 +9219,16 @@ } }, "interface_nets": { - "mipi_phy_if_5_1": { + "ps8_0_axi_periph_M16_AXI": { "interface_ports": [ - "mipi_phy_if_5", - "mipi/mipi_phy_if_5" + "ps8_0_axi_periph/M16_AXI", + "user_i2c/S_AXI3" + ] + }, + "ps8_0_axi_periph_M06_AXI": { + "interface_ports": [ + "ps8_0_axi_periph/M06_AXI", + "mipi/S_AXI10" ] }, "axi_iic_4_IIC": { @@ -8806,10 +9237,16 @@ "mipi/iic_rtl_5" ] }, - "ps8_0_axi_periph_M06_AXI": { + "mipi_phy_if_5_1": { "interface_ports": [ - "ps8_0_axi_periph/M06_AXI", - "mipi/S_AXI10" + "mipi_phy_if_5", + "mipi/mipi_phy_if_5" + ] + }, + "MIPI_Interfaces_M00_AXI1": { + "interface_ports": [ + "zynq_ultra_ps_e_0/S_AXI_HPC1_FPD", + "mipi/M00_AXI1" ] }, "ps8_0_axi_periph_M12_AXI": { @@ -8890,12 +9327,6 @@ "mipi/S_AXI1" ] }, - "MIPI_Interfaces_M00_AXI1": { - "interface_ports": [ - "zynq_ultra_ps_e_0/S_AXI_HPC1_FPD", - "mipi/M00_AXI1" - ] - }, "user_i2c_qwiic_rtl_2": { "interface_ports": [ "qwiic_rtl_2", @@ -8997,6 +9428,12 @@ "ps8_0_axi_periph/M02_AXI", "mipi/S_AXI2" ] + }, + "user_i2c_IIC_0": { + "interface_ports": [ + "usb_smbus_rtl_0", + "user_i2c/IIC_0" + ] } }, "nets": { @@ -9033,7 +9470,8 @@ "zynq_ultra_ps_e_0/saxihpc1_fpd_aclk", "mipi/video_aclk", "user_i2c/s_axi_aclk", - "Debug/CLK" + "Debug/CLK", + "ps8_0_axi_periph/M16_ACLK" ] }, "rst_ps8_0_49M_peripheral_aresetn": { @@ -9059,7 +9497,8 @@ "ps8_0_axi_periph/M15_ARESETN", "mipi/video_aresetn", "user_i2c/s_axi_aresetn", - "Debug/resetn" + "Debug/resetn", + "ps8_0_axi_periph/M16_ARESETN" ] }, "zynq_ultra_ps_e_0_pl_resetn0": { @@ -9254,6 +9693,12 @@ "GPIO/dout", "zynq_ultra_ps_e_0/emio_gpio_i" ] + }, + "user_i2c_iic2intc_irpt3": { + "ports": [ + "user_i2c/iic2intc_irpt3", + "interrupts/In15" + ] } }, "addressing": { @@ -9340,6 +9785,11 @@ "address_block": "/user_i2c/qwiic_iic_2/S_AXI/Reg", "offset": "0x00800B0000", "range": "64K" + }, + "SEG_usb_smbus_0_Reg": { + "address_block": "/user_i2c/usb_smbus_0/S_AXI/Reg", + "offset": "0x0080100000", + "range": "64K" } } } diff --git a/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v b/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v index 00b393ad..95af3c10 100644 --- a/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v +++ b/ovc5/firmware/carrier_board/carrier_board.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v @@ -1,8 +1,8 @@ //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 -//Date : Tue Aug 24 12:08:48 2021 -//Host : jank-osrf running 64-bit Ubuntu 20.04.3 LTS +//Date : Mon Oct 18 14:51:09 2021 +//Host : luca-focal running 64-bit Ubuntu 20.04.3 LTS //Command : generate_target design_1_wrapper.bd //Design : design_1_wrapper //Purpose : IP block netlist @@ -64,7 +64,9 @@ module design_1_wrapper qwiic_rtl_1_scl_io, qwiic_rtl_1_sda_io, qwiic_rtl_2_scl_io, - qwiic_rtl_2_sda_io); + qwiic_rtl_2_sda_io, + usb_smbus_rtl_0_scl_io, + usb_smbus_rtl_0_sda_io); output [5:0]ENABLE; output [0:0]FRAME_END_0; output [0:0]FRAME_START_0; @@ -120,6 +122,8 @@ module design_1_wrapper inout qwiic_rtl_1_sda_io; inout qwiic_rtl_2_scl_io; inout qwiic_rtl_2_sda_io; + inout usb_smbus_rtl_0_scl_io; + inout usb_smbus_rtl_0_sda_io; wire [5:0]ENABLE; wire [0:0]FRAME_END_0; @@ -230,6 +234,14 @@ module design_1_wrapper wire qwiic_rtl_2_sda_io; wire qwiic_rtl_2_sda_o; wire qwiic_rtl_2_sda_t; + wire usb_smbus_rtl_0_scl_i; + wire usb_smbus_rtl_0_scl_io; + wire usb_smbus_rtl_0_scl_o; + wire usb_smbus_rtl_0_scl_t; + wire usb_smbus_rtl_0_sda_i; + wire usb_smbus_rtl_0_sda_io; + wire usb_smbus_rtl_0_sda_o; + wire usb_smbus_rtl_0_sda_t; design_1 design_1_i (.ENABLE(ENABLE), @@ -322,7 +334,13 @@ module design_1_wrapper .qwiic_rtl_2_scl_t(qwiic_rtl_2_scl_t), .qwiic_rtl_2_sda_i(qwiic_rtl_2_sda_i), .qwiic_rtl_2_sda_o(qwiic_rtl_2_sda_o), - .qwiic_rtl_2_sda_t(qwiic_rtl_2_sda_t)); + .qwiic_rtl_2_sda_t(qwiic_rtl_2_sda_t), + .usb_smbus_rtl_0_scl_i(usb_smbus_rtl_0_scl_i), + .usb_smbus_rtl_0_scl_o(usb_smbus_rtl_0_scl_o), + .usb_smbus_rtl_0_scl_t(usb_smbus_rtl_0_scl_t), + .usb_smbus_rtl_0_sda_i(usb_smbus_rtl_0_sda_i), + .usb_smbus_rtl_0_sda_o(usb_smbus_rtl_0_sda_o), + .usb_smbus_rtl_0_sda_t(usb_smbus_rtl_0_sda_t)); IOBUF iic_rtl_0_scl_iobuf (.I(iic_rtl_0_scl_o), .IO(iic_rtl_0_scl_io), @@ -413,4 +431,14 @@ module design_1_wrapper .IO(qwiic_rtl_2_sda_io), .O(qwiic_rtl_2_sda_i), .T(qwiic_rtl_2_sda_t)); + IOBUF usb_smbus_rtl_0_scl_iobuf + (.I(usb_smbus_rtl_0_scl_o), + .IO(usb_smbus_rtl_0_scl_io), + .O(usb_smbus_rtl_0_scl_i), + .T(usb_smbus_rtl_0_scl_t)); + IOBUF usb_smbus_rtl_0_sda_iobuf + (.I(usb_smbus_rtl_0_sda_o), + .IO(usb_smbus_rtl_0_sda_io), + .O(usb_smbus_rtl_0_sda_i), + .T(usb_smbus_rtl_0_sda_t)); endmodule diff --git a/ovc5/firmware/carrier_board/carrier_board.xpr b/ovc5/firmware/carrier_board/carrier_board.xpr index c28ae2a7..b1edbd63 100644 --- a/ovc5/firmware/carrier_board/carrier_board.xpr +++ b/ovc5/firmware/carrier_board/carrier_board.xpr @@ -3,7 +3,7 @@ - +