Improve generation of vector instructions

[boomanaiden154]

Currently, we only compile for base X86. It would be good to also have instructions from newer ISA extensions like AVX512 in the corpus. This will require some changes in the data collection methodology. Particularly, we need to add additional lowerings enabling specific target features so that we can enable the creation of blocks containing these instructions.

[boomanaiden154]

We also need additional opt runs as the middle end optimization pipeline can call into target transform info to decide on things like vector widths, which will vary depending upon the architecture that we enable.

We'll need to figure out how to limit the number of potential combinations (perhaps only running specific -marches with -O3 to prevent an explosion of the total number of combinations.